A fractional-N PLL (Phase Locked Loop) can lock the PLL with a division number after the decimal point by controlling the division number of the divider using a frequency division number control signal generated by a ΔΣ modulator.
Further, in a case where two fractional-N PLLs each having the same configuration are placed in parallel and each receive the same reference signal, by shifting one of division number control signals generated by the ΔΣ modulator, by the clock unit, to the other, a phase difference can be given between output signals of the two PLLs in accordance with the shift amount.
A pulse shift circuit disclosed in Non-patent Document 1 is known as a circuit to shift a frequency division number control signal generated by a ΔΣ modulator by the clock unit.
The conventional pulse shift circuit outputs a pulse signal at a timing shifted by the number of clocks intended with respect to a pulse signal outputted by a reference pulse circuit. The shift amount is determined by the clock difference between a reset signal to the reference pulse circuit and a reset signal to the pulse shift circuit. In other words, the conventional pulse shift circuit shifts the output timing of the pulse signal by shifting the reset timing of the pulse shift circuit with respect to the reset timing of the reference pulse circuit by the number of clocks corresponding to the shift amount. The reset signals are signals to return the internal devices of the pulse shift circuit or the reference pulse circuit to their initial value states.
In the conventional pulse shift circuit, because operation start timing after resetting the pulse shift circuit is delayed by the intended number of clocks with respect to operation start time after resetting the reference pulse circuit, the pulse signal outputted by the pulse shift circuit is outputted at a shifted timing by the intended number of clocks with respect to the pulse signal outputted by the reference pulse circuit.